產品關鍵詞：
STM32L151C,
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex?-
M4 with FPU core.
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Closely coupled NVIC gives low-latency interrupt processing
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Interrupt entry vector table address passed directly to the core
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Allows early processing of interrupts
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Processing of late arriving, higher-priority interrupts
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Support tail chaining
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Processor state automatically saved
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Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.15
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected
to the 16 external interrupt lines
產品關鍵詞：
STM32L151C,
![STM8S103F3P6 管裝/STM32L151]()
